The present application relates to power devices, and more particularly to power devices with vertical or lateral current flow through a drift region.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
High voltage devices such as Diodes, JFETs, IGBTs and MOSFETs are widely used as switching devices in many electronic applications. In order to minimize the conduction power loss in power MOSFETs, it is desirable to have a low specific on-resistance (RSP or R*A), which is the product of the on-resistance of the MOSFET multiplied by the active die area. In general, the on-resistance of a power MOSFET is dominated by the channel and drift region resistances. In recent years, the so-called superjunction structure has been developed to reduce the drift region resistance. A superjunction device is constructed by paralleling highly doped alternating p-type and n-type layers or pillars. For a given breakdown voltage, the doping concentration of the n-type pillars (the n-type drift region), can be significantly higher than that of a conventional drift region, provided that the total charge of the n-type pillar is balanced with the charge in the p-type pillar. In order to fully realize the benefit of the superjunction technology, it is desirable to pack many pillars in a given area to achieve a lower RSP. However, the minimum widths of the n-type and p-type pillars which can be reached in device manufacturing set a limit on the minimum cell pitch as well as on scaling of the device.
Recently, some of the present inventors have addressed this issue by incorporating permanent positive charge (QF) in trenches filled with dielectric material such as silicon oxide. FIGS. 1 and 2 generally illustrate these concepts, and more detail can be found in published US Applications 20080191307, 20080164516, and 20080164518, all of which are hereby incorporated by reference.
FIG. 1 shows an example of a diode structure, in which frontside metallization 103 and backside metallization 102 provide low-resistance connections for cathode and anode, respectively. The semiconductor mass, in this example, is silicon, and has a p-type epitaxial layer 112 over an n+ substrate 110. A P+ doped region 114 provides good ohmic contact to the frontside metallization 103. Trenches 120 are filled (in this example) with a dielectric material 122, typically silicon dioxide. Permanent charge 124 is present near the sidewalls of the trenches 120. For example, such charge can be introduced by angle-implanting cesium ions into a thin grown oxide on the sidewalls of the trenches 120 before they are filled.
FIG. 2 shows one example of a trench transistor as described in the published applications referenced above. Here insulated polysilicon gate electrodes 230 are present in the upper parts of trenches 120, and the semiconductor structure near the front surface includes a p-type body region 240 which is contacted by a p+ body contact diffusion 242, as well as an n+ source region 244. Positive permanent charge 124 is present near the trench sidewalls, and provides improved charge balancing when the epitaxial layer 112 is depleted under reverse bias.
The permanent charge also forms an induced drift region by forming an inversion layer along the interface between the oxide and the P-type layer. Using this new concept, the scaling limitation due to inter-diffusion of p-type pillar and n-type pillar can be eliminated. Consequently, a small cell pitch and high packing density of pillars (and of channel area) can be realized, to thereby reduce the device total on resistance and RSP.
As the trench depth increases and cell pitch reduces, the trench depth to width aspect ratio increases. High aspect ratio trenches are more difficult to fill with dielectric material, and manufacturing the device becomes a problem. Furthermore, as the cell pitch is reduced and the cell density increases, the associated intrinsic capacitances of the device also increase undesirably. These include the gate-to-source and gate-to-drain capacitances Cgs and Cgd. The corresponding gate-source and gate-drain charges Qgs and Qgd also increase.